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HA-2510/883
High Slew Rate Operational Amplifier
Description
The HA-2510/883 is a high performance operational amplifier which sets the standards for maximum slew rate and wide bandwidth operation in moderately powered, internally compensated, monolithic devices. In addition to excellent dynamic characteristics, this dielectrically isolated amplifier also offers low offset current and high input impedance. The 50V/s minimum slew rate and fast settling time of the HA-2510/883 are ideally suited for high speed D/A, A/D, and pulse amplification designs. The HA-2510/883's superior bandwidth and 750kHz minimum full power bandwidth are extremely useful in RF and video applications. To insure compliance with slew rate and transient response specifications, all devices are 100% tested for AC performance characteristics over full temperature limits. To improve signal conditioning accuracy, the HA-2510/883 provides a maximum offset current of 25nA and a minimum input impedance of 50M, both at 25oC, as well as offset voltage adjust capability.
October 26, 2004
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * High Slew Rate . . . . . . . . . . . . . . . . . . . . . . .50V/s (Min) 65V/s (Typ) * Wide Power Bandwidth . . . . . . . . . . . . . . . 750kHz (Min) * Low Offset Current . . . . . . . . . . . . . . . . . . . . 25nA (Min) 10nA (Typ) * High Input Impedance . . . . . . . . . . . . . . . . . 50M (Min) 100M (Typ) * Wide Small Signal Bandwidth. . . . . . . . . . .12MHz (Typ) * Fast Settling Time (0.1% of 10V Step) . . . . 250ns (Typ) * Low Quiescent Supply Current . . . . . . . . . . 6mA (Max) * Internally Compensated For Unity Gain Stability
Applications
* Data Acquisition Systems * RF Amplifiers * Video Amplifiers * Signal Generators * Pulse Amplification
Ordering Information
PART NUMBER HA7-2510/883 TEMP. RANGE (oC) -55 to 125 PACKAGE 8 Ld CERDIP PKG. NO. F8.3A
Pinout
HA-2510/883 (CERDIP) TOP VIEW
BAL -IN +IN V-
1 2 3 4 +
8 7 6 5
COMP V+ OUT BAL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002, 2004. All Rights Reserved
Spec Number
1
511003-883 FN3697.3
HA-2510/883
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . 40V Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to VPeak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V
Thermal Information
Thermal Resistance (Typical, Note 1) JA JC CERDIP Package . . . . . . . . . . . . . . . . . . 120oC/W 30oC/W Package Power Dissipation Limit at 75oC for TJ 175oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870mW Package Power Dissipation Derating Factor Above 75oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mW/oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V VINCM 1/2 (V+ - V-) RL 2k
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VSUPPLY = 15V, RSOURCE = 100, RLOAD = 500k, VOUT = 0V, Unless Otherwise Specified. PARAMETER Input Offset Voltage SYMBOL VIO VCM = 0V CONDITIONS GROUP A SUBGROUPS 1 2, 3 Input Bias Current +IB VCM = 0V, +RS = 100k, -RS = 100 1 2, 3 -IB VCM = 0V, +RS = 100, -RS = 100k 1 2, 3 Input Offset Current IIO VCM = 0V, +RS = 100k, -RS = 100k 1 2, 3 Common Mode Range +CMR V+ = 5V, V- = -25V 1 2, 3 -CMR V+ = 25V, V- = -5V 1 2, 3 Large Signal Voltage Gain +AVOL VOUT = 0V and +10V, RL = 2k 4 5, 6 -AVOL VOUT = 0V and -10V, RL = 2k 4 5, 6 Common Mode Rejection Ratio +CMRR VCM = +10V, V+ = +5V, V- = -25V, VOUT = -10V VCM = -10V, V+ = +25V, V- = -5V, VOUT = +10V 1 2, 3 1 2, 3 TEMP (oC) 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 MIN -8 -18 -200 -400 -200 -400 -25 -50 +10 +10 10 7.5 10 7.5 80 80 80 80 MAX 8 10 200 400 200 400 25 50 -10 -10 UNITS mV mV nA nA nA nA nA nA V V V V kV/V kV/V kV/V kV/V dB dB dB dB
-CMRR
Spec Number 2
511003-883
HA-2510/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: VSUPPLY = 15V, RSOURCE = 100, RLOAD = 500k, VOUT = 0V, Unless Otherwise Specified. PARAMETER Output Voltage Swing SYMBOL +VOUT RL = 2k CONDITIONS GROUP A SUBGROUPS 4 5, 6 -VOUT RL = 2k 4 5, 6 Output Current +IOUT VOUT = -10V 4 5, 6 -IOUT VOUT = +10V 4 5, 6 Quiescent Power Supply Current +ICC VOUT = 0V, IOUT = 0mA VOUT = 0V, IOUT = 0mA VSUP = 10V, V+ = +20V, V- = -15V, V+ = +10V, V- = -15V VSUP = 10V, V+ = +15V, V- = -20V, V+ = +15V, V- = -10V 1 2, 3 1 2, 3 1 2, 3 -PSRR 1 2, 3 Offset Voltage Adjustment +VIOAdj Note 2 1 2, 3 -VIOAdj Note 2 1 2, 3 NOTE: 2. Offset adjustment range is [VIO (Measured) 1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VSUPPLY = 15V, RSOURCE = 50, RLOAD = 2k, CLOAD = 50pF, AVCL = +1V/V, Unless Otherwise Specified. PARAMETER Slew Rate SYMBOL +SR CONDITIONS VOUT = -5V to +5V, 25% +SR 75% GROUP A SUBGROUPS 7 8A, 8B -SR VOUT = +5V to -5V, 75% -SR 25% 7 8A, 8B TEMP (oC) 25 125, -55 25 125, -55 MIN 50 45 50 45 MAX UNITS V/s V/s V/s V/s TEMP (oC) 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 MIN 10 10 10 7.5 -6 -6.5 80 80 80 80 VIO-1 VIO-1 VIO+1 VIO+1 MAX -10 -10 -10 -7.5 6 6.5 UNITS V V V V mA mA mA mA mA mA mA mA dB dB dB dB mV mV mV mV
-ICC
Power Supply Rejection Ratio
+PSRR
Spec Number 3
511003-883
HA-2510/883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: VSUPPLY = 15V, RSOURCE = 50, RLOAD = 2k, CLOAD = 50pF, AVCL = +1V/V, Unless Otherwise Specified. PARAMETER Rise and Fall Time SYMBOL tr CONDITIONS VOUT = 0 to +200mV, 10% tr 90% GROUP A SUBGROUPS 7 8A, 8B tf VOUT = 0 to -200mV, 10% tf 90% 7 8A, 8B Overshoot +OS VOUT = 0 to +200mV 7 8A, 8B -OS VOUT = 0 to -200mV 7 8A, 8B TEMP (oC) 25 125, -55 25 125, -55 25 125, -55 25 125, -55 MIN MAX 50 60 50 60 40 50 40 50 UNITS ns ns ns ns % % % %
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Characterized at: VSUPPLY = 15V, RLOAD = 2k, CLOAD = 50pF, Unless Otherwise Specified. PARAMETER Differential Input Resistance Full Power Bandwidth Minimum Closed Loop Stable Gain Quiescent Power Consumption NOTES: 3. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. 4. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2VPEAK). 5. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.) TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters Group A Test Requirements Groups C and D Endpoints NOTE: 6. PDA applies to Subgroup 1 only. SUBGROUPS (SEE TABLES 1 AND 2) 1 1 (Note 6), 2, 3, 4, 5, 6, 7, 8A, 8B 1, 2, 3, 4, 5, 6, 7, 8A, 8B 1 SYMBOL RIN FPBW VCM = 0V VPEAK = 10V RL = 2k, CL = 50pF VOUT = 0V, IOUT = 0mA CONDITIONS NOTES 3 TEMP (oC) 25 MIN 50 MAX UNITS M
3, 4
25
750
-
kHz
CLSG
3
-55 to 125
1
-
V/V
PC
3, 5
-55 to 125
-
195
mW
Spec Number 4
511003-883
HA-2510/883 Die Characteristics
DIE DIMENSIONS: 65 mils x 57 mils x 19 mils 1650m x 1450m x 483m METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA GLASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA WORST CASE CURRENT DENSITY: 0.3 x 105 A/cm2 SUBSTRATE POTENTIAL (Powered Up): Unbiased TRANSISTOR COUNT: HA-2510/883: 40 PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-2510/883
+IN -IN BAL
COMP
V-
V+
BAL
OUT
5
HA-2510/883 Burn-In Circuit
HA7-2510/883
1 R1 2 3 VD2 C2 4
8
+
7 6 5 C3 C1 D1
V+
R1 = 1M, 5%, 1/4W (Min) C1 = C2 = 0.01F/Socket (Min) or 0.1F/Row (Min) C3 = 0.01F/Socket (10%) D1 = D2 = 1N4002 or Equivalent/Board |(V+) - (V-)| = 30V
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HA-2510/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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